K-ADD @ FPGA 2022

Table of Contents

link: Multi-input Serial Adders @ FPGA 2022

TL;DR: This paper proposes a new functional unit K-ADD to replace the K-LUT unit in FPGA to accelerate sparse integer matrix multiplication.


Previous Work

See Spatial Sparse Matrix Multiplier.

Note that the sparsity of this work only helps saving energy, not area/time.

LUTs and Clusters

Suppose FPGA LUT size (number of inputs) is \(K\),

  • smaller \(K\) is more area efficient
  • larger \(K\) reduces delay of routable interconnect, which improves performance.


cluster size
number of LUTs inside a cluster (block).
Ultrascale clb

Large cluster sizes of earlier FPGAs may not be optimal.

K-ADD functional unit

Author: expye(Zihao Ye)

Email: expye@outlook.com

Date: 2022-08-06 Sat 00:00

Last modified: 2022-12-27 Tue 07:18

Licensed under CC BY-NC 4.0