Tomasulo and HPSm
Tomasulo is the classic architecture that allow out-of-order execution when there are multiple execution units. Tomasulo designs a Reservation Buffer/CDB structure that maintains a sliding window of dataflow, and register renaming mechanism to analyze the data dependency at hardware level. HPSm further enhance Tomasulo with Reorder Buffer to enable precise handling of exceptions and branch prediction miss.
Questions:
- Why not offload the analysis on WAW and WAR to compilers? (e.g. Compilers first performs SSA which eliminates all WAW/WAR, then allocates register to reuse resources, if the hardware design is known compilers, we can avoid WAW/WAR at compile time, rather then register renaming).
- The performance of software level scheduling vs hardware scheduling (Mark suggest an ASPLOS paper: https://dl.acm.org/doi/10.1145/2451116.2451143)
- How many Reservation Buffer do we need (RB/EU = 1:1/1:n/n:1)